1. Field of the Invention
The present invention relates generally to the field of digital data processing systems and, more particularly, to an apparatus and method of developing applications software for a multi-processor chip.
2. Background
The apparatus and method of developing software for a multi-processor chip provides a solution to developing applications software for a new multi-processor chip design, with fast simulation.
Conventional development of applications software for a new processor chip requires a software simulation model of the entire new chip design, and then the applications software is run on the model of the chip. Simulation in this way may be slow, due to the sheer quantity of design states that must be modeled for the chip.
As integrated circuit geometries scale with process technology, more area becomes available on a chip for new functions. New multi-processor chip designs are beginning to integrate processor designs from previous production processor chips, where a previous production processor is essentially lifted and inserted into a corner of the new multi-processor chip. The previous processors have highly detailed simulation models, such as a detailed gate-level model. Because the simulation models are highly detailed, the processor simulation models are highly computationally intensive and therefore relatively slow to run.
Newer processor designs are known that have two simulation models. One version of the simulation model is the previously described detailed simulation model. The other version is a high-level, fast, cycle-accurate model. By simulating with the high-level model, high-speed simulation of the chip designs can be achieved.
When new multi-processor chips are designed that use previously designed processors and newer processors on one chip, high-speed simulation of the entire multi-processor chip may not be achieved because no high-speed simulation model exists for the previous processors. This causes a bottleneck in the development of the applications software.
Further, because the new multi-processor chips contain multiple processors, communications need to be tested between the processors, which involve interrupt and signaling mechanisms. The previous design chip sections do not have this hardware.
Another problem is simulation of memory access. Initialization of tables in memory can take as long as forty-five minutes. A need exists to circumvent this startup delay for most tests.
A need therefore exists for a solution to develop and test applications software on a new multi-processor chip design that uses previous processors and newer processors, with fast simulation and minimal resources expended to create the simulation model. Furthermore, the solution should provide a way to test communications between processors and fast simulation of memory access.